It is known that a trouble, a malfunction and so on of a semiconductor integrated circuit are caused in the semiconductor integrated circuit used generally, when a charged particle having a relatively large energy hits to the semiconductor integrated circuit, resulting in occurrence of an important error.
As an example of such an error, SEL (Single Event Latchup), SEU (Single Event Upset), SET (Single Event Transient), and so on are known.
The cause of these errors is a charged particle and a radiation. Therefore, in an artificial satellite working in a space, a radiation camera and so on, it is necessary to constrain an error due to the radiation so that the built-in semiconductor integrated circuit works normally.
In conjunction with the above, an invention of a semiconductor circuit is disclosed in Patent Literature 1 (JP_2010-183087A). The semiconductor circuit specified in Patent Literature 1 is composed of a first circuit block and a second circuit block. Here, the first circuit block is formed for a plurality of PMOS transistors to be connected in serial or to be connected to a parallel circuit having one PMOS transistor. The second circuit block is formed for a plurality of NMOS transistors to be connected in serial or to be connected to a parallel circuit having one NMOS transistor. In the semiconductor circuit described in Patent Literature 1, a connection point between the first circuit block and the second circuit block is connected with an output terminal and the gates of all the PMOS transistors and the gates of all the NMOS transistors are connected to a common input terminal.
In case of Patent Literature 1, the redesigning of the semiconductor integrated circuit itself becomes necessary. Therefore, this technique is disadvantageous on both of a development period and a cost.